1 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter january 2002 2002 integrated device technology, inc. dsc-5821/4 c industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. functional block diagram qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter description: the qs5lv931 clock driver uses an internal phase locked loop (pll) to lock low skew outputs to a reference clock input. six outputs are available: q 0 ?q 4 , q/2. careful layout and design ensure <300ps skew between the q 0 ?q 4 , and q/2 outputs. the qs5lv931 includes an internal rc filter which provides excellent jitter characteristics and eliminates the need for external components. various combinations of feedback and a divide-by-2 in the vco path allow applications to be customized for linear vco operation over a wide range of input sync frequencies. the pll can also be disabled by the pll_en signal to allow low frequency or dc testing. the qs5lv931 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. in the qsop package, the qs5lv931 clock driver represents the best value in small form factor, high-performance clock management products. for more information on pll clock driver products, see application note an-227. features: ? 3.3v operation ? jedec lvttl compatible level ? clock input is 5v tolerant ? q outputs, q/2 output ? <300ps output skew, q 0 ?q 4 ? outputs 3-state and reset while oe/ rst low ? pll disable feature for low frequency testing ? internal loop filter rc network ? internal vco/2 option ? balanced drive outputs 24ma ? esd >2000v ? 80mhz maximum frequency ? available in qsop package r d q q 0 r d q q 1 r d q q 2 r d q q 3 r d q q 4 r d q q/ 2 0 1 1 0 /2 vco loop filter phase detector freq_sel feedback sync pll_en oe/rst q
2 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter pin configuration note: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. absolute maximum ratings (1) symbol description max unit av dd /v dd supply voltage to ground ?0.5 to +7 v dc input voltage v in ?0.5 to +5.5 v maximum power dissipation (t a = 85c) 0.5 w t stg storage temperature range ?65 to +150 c qsop top view capacitance (t a = +25c, f = 1mhz, v in = 0v) pins typ. max. unit c in 34pf c out 45pf pin description pin name i/o description sync i reference clock input freq_sel i vco frequency select. for choosing optimal vco operating frequency depending on input frequency. high is for higher f requencies, low is for lower frequencies. feedback i pll feedback input which is connected to either a q or a q/2 output. external feedback provides flexibility for different outp ut frequency relationships. see the frequency selection table for more information. q 0 -q 4 o clock outputs q/2 o clock output. matched in phase, but frequency is half the q frequency. oe/ rst i output enable/asynchronous reset. resets all output registers. when 0, all outputs are held in a tri-stated condition. when 1, outputs are enabled. pll_en i pll enable. enables and disables the pll. allows the sync input to be single-stepped for system debug. v dd ? power supply for output buffers av dd ? power supply for phase lock loop and other internal circuitries gnd ? ground supply for output buffers agnd ? ground supply for phase lock loop and other internal circuitries output frequency specifications industrial: t a = ?40c to +85c, av dd /v dd = 3.3v 0.3v symbol description ? 50 ? 66 ? 80 units f max_q max frequency, q 0 - q 4 , 50 66 80 mhz f max_q/2 max frequency, q/2 25 33 40 mhz f min_q min frequency, q 0 - q 4 10 10 10 m h z f min_q/2 min frequency, q/2 5 5 5 mhz 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd oe/rst feedback av dd agnd sync freq_sel gnd q 1 q 4 q/2 gnd q 3 q 2 gnd pll_en gnd q 1 v dd v dd
3 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter power supply characteristics symbol parameter test conditions typ. max. unit i ddq quiescent power supply current v dd = max., oe/ rst = low, ? 1 ma sync = low, all outputs unloaded i dd power supply current per input high v dd = max., v in = 3v 1 30 a i ddd dynamic power supply current per output v dd = max., c l = 0pf 0.2 0.3 a/mhz frequency selection table sync (mhz) output used for (allowable range) (1) output frequency relationships freq_sel feedback min. max q/2 q 0 - q 4 high q/2 f min_q/2 f max _q/2 sync sync x 2 high q 0 -q 4 f min_q f max _q sync / 2 sync low q/2 f min_q/2 /2 f max _q/2 /2 sync sync x 2 low q 0 -q 4 f min_q /2 f max _q /2 sync / 2 sync note: 1. operation in the specified sync frequency range guarantees that the vco will operate in its optimal range of 20mhz to f max_q x2. operation with sync inputs outside specified frequency ranges may result in out-of-lock outputs. freq_sel only affects vco frequency and does not affect output frequencies. dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, av dd /v dd = 3.3v 0.3v symbol parameter conditions min. typ. max. unit v ih input high voltage guaranteed logic high level 2 ? ? v v il input low voltage guaranteed logic low level ? ? 0.8 v v oh output high voltage i oh = ? 24ma v dd ? 0.6 ? ? v i oh = ? 100 av dd ? 0.2 ? ? v ol output low voltage v dd = min., i ol = 24ma ? ? 0.45 v v dd = min., i ol = 100 a ? ? 0.2 v h input hysteresis ? ? 100 ? mv i oz output leakage current v out = v dd or gnd, ? ? 5 a v dd = max., outputs disabled i in input leakage current av dd = max., v in = av dd or gnd ? ? 5 a input timing requirements symbol description (1) min. max. unit t r , t f maximum input rise and fall times, 0.8v to 2v ? 3 ns f i input clock frequency, sync (1) 2.5 f max _q mhz t pwc input clock pulse, high or low (2) 2?ns d h duty cycle, sync (2) 25 75 % notes: 1. see output frequency and frequency selection tables for more detail on allowable sync input frequencies for different speed g rades with different feedback and freq_sel combinations. 2. where pulse witdh implied by d h is less than t wpc limit, t wpc limit applies
4 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter switching characteristics over operating range symbol parameter (1) min. max. unit t skr output skew between rising edges, q 0 -q 4 and q/2 (2) ? 300 ps t skf output skew between falling edges, q 0 -q 4 and q/2 (2) ? 300 ps t pw pulse width, q 0 -q 4 , q/2 outputs, 80mhz t cy /2 ? 0.4 t cy /2 + 0.4 ns t j cycle-to-cycle jitter (4) ? 0.15 0.15 ns t pd sync input to feedback delay (5) ? 500 500 ps t lock sync to phase lock ? 10 ms t pzh output enable time, oe/ rst low to high (3) 014ns t pzl t phz output disable time, oe/ rst high to low (3) 014ns t plz t r, t f output rise/fall times, 0.8v ~ 2v 0.3 2 ns notes: 1. see test loads and waveforms for test load and termination. 2. skew specifications apply under identical environments (loading, temperature, v dd , device speed grade). 3. measured in open loop mode pll_en = 0. 4. jitter is characterized with q output at 20mhz. see frequency selection table for information on proper freq_sel level for s pecified input frequencies. 5. t pd measured at device inputs at 0.5v dd , q output at 80mhz.
5 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter 300 30pf 300 6.0v output v dd output 1.0ns 1.0ns 2.0v 0.8v 3.0v 0v v th = 0.5v dd t r t f 0v 0.5v dd t pw control input enable disable 3v 0v 3.0v 0v 0.5v dd output normally low output normally high switch open switch closed t pzh 0.3v 0.3v t pzl t plz t phz 0.5v dd v oh v ol 100 100 2.0v 0.8v 3.0v 0.5v dd ac test loads and waveforms test circuit 1 cmos input test waveform cmos output waveform test circuit 2 test circuit 1 is used for output enable/disable parameters. test circuit 2 is used for all other timing parameters. enable and disable times
6 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter ac timing diagram t pd sync feedback q q 0 -q 4 q/2 t j t skf t skall t skr notes: 1. ac timing diagram applies to q output connected to feedback . 2. all parameters are measured at 0.5v dd.
7 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter pll operation the phase locked loop (pll) circuit included in the qs5lv931 provides for replication of incoming sync clock signals. any manipulation of that signal, such as frequency multiplying, is performed by digital logic following the pll (see the block diagram). the key advantage of the pll simplified diagram of qs5lv931 feedback the phase difference between the output and the input frequencies feeds the vco which drives the outputs. whichever output is fed back, it will stabilize at the same frequency as the input. hence, this is a true negative feedback closed loop system. in most applications, the output will optimally have zero phase shift with respect to the input. in fact, the internal loop filter on the qs5lv931 typically provides within 150ps of phase shift between input and output. circuit is to provide an effective zero propagation delay between the output and input signals. in fact, adding delay circuits in the feedback path, ?propagation delay? can even be negative! a simplified schematic of the qs5lv931 pll circuit is shown below. if the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. the respective output used for feedback will be advanced by the amount of delay in the feedback path. all other outputs will retain their proper relationships to that output. q/2 q vco/2 /2 phase detector input
8 industrial temperature range qs5lv931 3.3v low skew cmos pll clock driver with integrated loop filter ordering information qs xx speed 5lv931 3.3v low skew cmos pll clock driver with inte g rated loop filter xxxx device type x package 50 66 80 50mhz max. frequency 66mhz max. frequency 80mhz max. frequency q qg quarter size outline package qsop - green x process blank industrial (-40c to +85c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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